HY5S7B2ALFP-6 Datasheet, Hynix Semiconductor

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HY5S7B2ALFP-6 Features and benefits

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* Standard SDRAM Protocol Clock Synchronization Operation - All the commands registered on positive edge of basic input clock (CLK) MULTIBANK OPERATION - .

HY5S7B2ALFP-6 Application

which requires large memory density and high bandwidth. It is organized as 4banks of 4,194,304x32. Mobile SDRAM is a typ.

HY5S7B2ALFP-6 Description

and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.2 / Nov. 2008 1 11 512Mbit (16Mx32bit) Mobile SDR Memory HY5S7B2ALF(P) Series Document Title 4Bank.

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