HY5S7B2ALFP-6 Datasheet PDF - Hynix Semiconductor 512M (16Mx32bit) Mobile SDRAM Specs

HY5S7B2ALFP-6 - 512M (16Mx32bit) Mobile SDRAM

Datasheet Summary

Description

and is subject to change without notice.

Hynix does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Features

Standard SDRAM Protocol Clock Synchronization Operation - All the commands registered on positive edge of basic input clock (CLK).

Datasheet Details

Part number	HY5S7B2ALFP-6
Manufacturer	Hynix Semiconductor
File Size	1.84 MB
Description	512M (16Mx32bit) Mobile SDRAM
Datasheet	HY5S7B2ALFP-6 Datasheet
Additional preview pages of the HY5S7B2ALFP-6 datasheet.

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Full PDF Text Transcription

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512MBit MOBILE SDR SDRAMs based on 4M x 4Bank x32 I/O Specification of 512M (16Mx32bit) Mobile SDRAM Memory Cell Array - Organized as 4banks of 4,194,304 x32 This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.2 / Nov. 2008 1 11 512Mbit (16Mx32bit) Mobile SDR Memory HY5S7B2ALF(P) Series Document Title 4Bank x 4M x 32bits Synchronous DRAM Revision History Revision No. 0.1 1.0 1.1 1.2 Initial Draft Release Insert (Page10) DPD specification [IDD7 : 10uA min] Correct device height (page 53) History Draft Date Nov. 2006 May. 2007 July. 2007 Nov. 2008 Remark Preliminary Rev 1.2 / Nov.

Published: Mar 2, 2011 |